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Maxim > 方案 > 网络集线器、交换机和路由器

时钟恢复

数据资料
显示 标题/型号 关键优势
QV  PDF 单/双/四/八通道TDM-Over-Packet芯片
DS34T101, DS34T102, DS34T104, DS34T108

支持包交换网络的CESoPSN、SAToP和TDMoIP传输，可支持8个E1/T1端口
QV  PDF Stratum 2/3E/3时钟卡IC
DS3101

符合SONET/SDH Stratum 3/3E标准的时钟卡IC
QV  PDF Stratum 3/3E/3时钟卡IC
DS3100

完备的单芯片SONET/SDH时钟卡方案
QV  PDF 50MHz至122.88MHz VCXO
DS4077
QV  PDF 多输出网络时钟发生器
MAX9489

提供多时钟输出的时钟发生器，用于网络路由器
QV  PDF T1/E1/J1 BITS单元
DS26503
QV  PDF T1/E1/J1/64KCC BITS单元
DS26502

业内唯一的64kHz复合时钟收发器
QV  PDF 1:5差分(LV)PECL/(LV)ECL/HSTL时钟和数据驱动器
MAX9316A

1:5差分(LV) PECL/(LV) ECL/HSTL时钟、数据驱动器，用于时钟与数据分配
QV  PDF 差分5:1或4:1 ECL/PECL多路复用器，带有单/双输出缓冲器
MAX9386, MAX9387, MAX9388

业内首款2.5GHz LVECL/LVPECL复用器
QV  PDF 4端口LVDS和LVTTL至LVDS转发器
MAX9169, MAX9170

脉冲偏差最小的4端口、LVDS/LVTTL至LVDS转接器
QV  PDF 1至5 LVPECL/LVCMOS输出时钟和数据驱动器
MAX9324
QV  PDF 低功耗、结构紧凑的2.5Gbps/2.7Gbps时钟恢复与数据再定时IC
MAX3873A
QV  PDF 四路T1/E1/J1收发器
DS21Q55, DS21Q55N
QV  PDF 622Mbps、3.3V时钟恢复与数据再定时IC，带有限幅放大器
MAX3676

高性能、低功耗622Mbps CDR



Key Specifications:  Clock and Data Recovery
Part Number Functions Target Oper. Range
(Gbps)		 Data Rate
(Mbps)		 Data Rate
(Mbps)		 Multirate VSUPPLY
(V)		 ICC
(mA)		 I/O Type Input Sens.
(mV)		 Package/Pins Oper. Temp.
(°C)
min max typ
MAX3873A  CDR 1 to 4.5 2488 2670 Yes 3.3 79 CML 50
QFN/20
TQFN/20
 -40 to +85
MAX3676  <1 622 622 No
3.3
5
 65 PECL -
TQFP/32
See All Clock and Data Recovery (8)

Key Specifications:  Clock Generators
Part Number Applications fIN
(MHz)		 fIN
(MHz)		 fOUT
(MHz)		 fOUT
(MHz)		 Fixed or Continuous Frequency Output Levels Out-
puts		 PLLs Program-
mability		 Spread Spectrum Output Jitter
(ps)		 VSUPPLY
(V)		 Package/Pins
min max min max RMS
MAX9489 
Ethernet
General Purpose
 10 25 25 133.3 Fixed LVCMOS 15 2 I2C No 48 3.3
TQFN/32
See All Clock Generators (25)

Key Specifications:  T/E Carrier & Packetized Products
Part Number Transmission Standard Functions Channels In-to-Out Clocks
(MHz)		 VSUPPLY
(V)		 EV Kit RoHS Available Package/Pins Smallest Available Pckg.
(mm2)
max w/pins
DS26502 
64kHz - G.703 II.1 Japanese 64kHz Clock
64kHz - G.703 II.2 Japanese 6312kHz Clock
64kHz Composite Clock - G.703 Level A
T1/E1/J1
 BITS Element 1
0.064
1.544
2.048
6.312
19.44
 3.3 Yes No
LQFP/64
 148.8
DS26503  T1/E1/J1
1.544
2.048
6.312
 See Data Sheet
See Data Sheet/
 -
See All T/E Carrier & Packetized Products (102)

Key Specifications:  High-Speed Interconnect (Differential Signaling)
Part Number Features Signal Type Signal Type Functions Rx Tx Data Rates
(Mbps)		 tPD
(ps)		 VSUPPLY
(V)
Rx Tx max
MAX9169  Fail-Safe Inputs LVDS LVDS Fan-Out Buffer 1 4 630 4200 3.3
MAX9170  Fail-Safe Inputs
LVCMOS
LVTTL
 LVDS
Fan-Out Buffer
Level Translator
 1 4 630 4200 3.3
MAX9316A 
Fail-Safe Inputs
Selectable Single Ended or Differential Input
Synchronous Output Enable
ECL
HSTL
LVECL
LVPECL
PECL
ECL
LVECL
LVPECL
PECL
 Fan-Out Buffer 2 5 - 520
3.3
5
MAX9386  Fail-Safe Inputs
ECL
LVECL
LVPECL
PECL
ECL
LVECL
LVPECL
PECL
 Multiplexer 5 1 - 431
3.3
5
MAX9387  Fail-Safe Inputs
ECL
LVECL
LVPECL
PECL
ECL
LVECL
LVPECL
PECL
 Multiplexer 5 2 - 431
3.3
5
MAX9388  Fail-Safe Inputs
ECL
LVECL
LVPECL
PECL
ECL
LVECL
LVPECL
PECL
 Multiplexer 4 1 - 431
3.3
5
MAX9324 
Fail-Safe Inputs
Synchronous Output Enable
 LVPECL
CMOS
LVPECL
LVTTL
 Fan-Out Buffer 1 5 - 600 3.3
See All High-Speed Interconnect (Differential Signaling) (133)

Key Specifications:  Oscillator Modules
Part Number Freq. Osc. Type Tuning Adjustment Type Freq. Output Type Frequency Stability
(±ppm/yr)		 Frequency Stability
(±ppm/yr)		 Frequency Stability
(±ppm)		 VSUPPLY
(V)
-40 to +85°C vs. VCC vs. Aging
DS4077  77.76MHz XO Voltage
LVCMOS
LVDS
 20 -3.5 to +11.5 (max) 10 (0-10 Years) 3.3 ±5%
See All Oscillator Modules (28)

Key Specifications:  Timing Card and Line Card ICs
Part Number Indep. DPLLs Input Clocks Diff. Input Clocks Output Clocks Diff. Output Clocks fCLKIN fCLKOUT DS1/E1/J1 Rcvrs. DS1/E1/J1 Xmtrs. DPLL BW
(Hz)		 DPLL BW
(Hz)		 Smallest Available Pckg.
(mm2)
min max max w/pins
DS3100  2 14 2 11 3
2kHz and 4kHz
N x 19.44MHz
N x 8kHz up to 155.52MHz
N x DS1
N x E1
2kHz
6.48MHz
8kHz
25.00MHz
51.84MHz
62.5MHz
125.00MHz
155.52MHz
311.04MHz
DS3
E3
N x 19.44MHz
N x DS1
N x DS2
N x E1
 2 2 0.0005 70 289
DS3101  0 0
See All Timing Card and Line Card ICs (6)

Key Specifications:  TDM-Over-Packet
Part Number Integrated T1/E1 LIU+Framer T1/E1/Serial Streams T3/E3, STS-1 Serial Ports Mapping Methods PSN Encapsulation Protocols 10/100 MAC Interface Processor Interface Package/Pins Smallest Available Pckg.
(mm2)		 RoHS Available
max w/pins
DS34T101  1 1 1
AAL1
CESoPSN
HDLC
SAToP
Structured
Structured with CAS
TDMoIP
Unstructured
L2TPv3 (IPv4, IPv6)
MEF-8
MPLS
RTP
UDP (IPv4, IPv6)
MII
RMII
SSMII
16-Bit
32-Bit
SPI
BGA/484
 529 Yes
DS34T102  2 2
BGA/484
DS34T104  4 4
BGA/484
DS34T108  8 8
BGA/484
See All TDM-Over-Packet (9)



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