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MAX3640EVKIT
MAX3640评估板


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概述
完整的数据资料 (PDF, 440kB)
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The MAX3640 evaluation kit (EV kit) is an assembled surface-mount demonstration board that provides easy evaluation of the MAX3640 622Mbps low-voltage differential signal (LVDS), dual 4:2 asynchronous crosspoint switch. The board includes an extra transmission line for characterization purposes.

The MAX3640 EV kit operates from a single +3.3V power supply and includes all external components necessary to interface with the LVDS inputs and outputs.

The LVDS inputs (DIA1–DIA4 and DIB1–DIB4) are internally terminated with 100Ω differential input resistance and therefore require no external termination. Ensure that LVDS devices driving these inputs are not redundantly terminated. The LVDS outputs (DOA1–DOA4 and DOB1–DOB4) require a differential termination of 100 ohms between the complementary outputs.

Connecting LVDS Outputs to 50Ω Oscilloscope Inputs
To monitor LVDS signals with 50Ω oscilloscope inputs, leave the coupling capacitors in series with the outputs and remove the differential load resistors (see R1–R8 in the Component List). If you are observing only one output with a 50Ω probe, balance the other output with a 50Ω terminator to ground.

Connecting LVDS Outputs to High-Impedance Oscilloscope Inputs
To monitor LVDS signals with high-impedance oscilloscope inputs, be sure the 100Ω differential load resistors between the differential outputs are installed (see R1–R8 in the Component List).

Layout Consideration
All relative input and output data lines have equal lengths to minimize channel-to-channel skew. The transmission lines all have 100Ω differential characteristic impedance between the complementary signal lines.

Jumpers
Jumpers JU1–JU4 allow the SEL1–SEL4 pins to be attached to VCC or GND. These pins set up the allocation of the input channels to the output channels. Jumpers JU6, JU7, and JU8 allow IN_SEL, ENA, and ENB to be attached to VCC or GND. Refer to Table 1 in the MAX3640 data sheet for more information on these pins.

关键特性   应用/使用
  • +3.3V Single Supply
  • Includes Transmission Line for Characterization
  • Fully Assembled and Tested Surface-Mount Board

 
  • ATM交换内核
  • 数字交叉连接
  • 高速并行链接
  • SONET/SDH背板
  • 系统互连

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    参考文献: 19-1732; Rev. 0; 2000-09-13
    本页最后一次更新: 2007-06-06


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