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MAX1003
低功耗、90Msps、双路6位ADC


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概述
完整的数据资料 (PDF, 128kB)
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The MAX1003 is a dual, 6-bit analog-to-digital converter (ADC) that combines high-speed, low-power operation with a user-selectable input range, an internal reference, and a clock oscillator. The dual parallel ADCs are designed to convert in-phase (I) and quadrature (Q) analog signals into two 6-bit, offset-binary-coded digital outputs at sampling rates up to 90Msps. The ability to directly interface with baseband I and Q signals makes the MAX1003 ideal for use in direct-broadcast satellite, VSAT, and QAM16 demodulation applications.

The MAX1003 input amplifiers feature true differential inputs, a -0.5dB analog bandwidth of 55MHz, and user-programmable input full-scale ranges of 125mVp-p, 250mVp-p, or 500mVp-p. With an AC-coupled input signal, matching performance between input channels is typically better than 0.1dB gain, 1/4LSB offset, and 0.5° phase. Dynamic performance is 5.85 effective number of bits (ENOB) with a 20MHz analog input signal, or 5.7 ENOB with a 50MHz signal.

The MAX1003 operates with +5V analog and +3.3V digital supplies for easy interfacing to +3.3V-logic-compatible digital signal processors and microprocessors. It comes in a 36-pin SSOP package.

关键特性   应用/使用
  • Two Matched 6-Bit ADCs
  • High Sampling Rate: 90Msps per ADC
  • Low Power Dissipation: 350mW
  • Excellent Dynamic Performance:
    • 5.85 ENOB with 20MHz Analog Input
    • 5.7 ENOB with 50MHz Analog Input
  • ±1/4LSB INL and DNL (typ)
  • Internal Bandgap Voltage Reference
  • Internal Oscillator with Overdrive Capability
  • 55MHz (-0.5dB) Bandwidth Input Amplifiers with True Differential Inputs
  • User-Selectable Input Full-Scale Range (125mVp-p, 250mVp-p, or 500mVp-p)
  • 1/4LSB Channel-to-Channel Offset Matching (typ)
  • 0.1dB Gain and 0.5° Phase Matching (typ)
  • Single-Ended or Differential Input Drive
  • Flexible, 3.3V, CMOS-Compatible Digital Outputs

 
  • 有线电视机顶盒
  • 直接转播卫星(DBS)接收机
  • VSAT接收器
  • 无线局域网(WLAN)

    Key Specifications:  High-Speed ADCs (> 5Msps)
    Part Number Input Chan. Resolution
    (bits)
    Sample Rate
    (Msps)
    AC Specs
    (MHz)
    SFDR
    (dBc)
    ENOB
    (bits)
    SINAD
    (dB)
    INL
    (±LSB)
    DNL
    (±LSB)
    Full Pwr. BW
    (MHz)
    ICC
    (mA)
    Smallest Available Pckg.
    (mm2)
    Price
    max ≥ @ fIN min min min min typ max w/pins See Notes
    MAX1003  2 6 90 20 38 5.85 37 0.25 0.25 55 84 163 $3.96 @1k
    查看所有High-Speed ADCs (> 5Msps) (77)

    图表
    MAX1003:功能框图
    功能框图

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    参考文献: 19-1236; Rev. 0; 1997-06-01
    本页最后一次更新: 2009-11-06


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