Abstract: Any independent delay line, in conjunction with a XOR gate, can be made into a clock frequency doubler by delaying the clock signal, and combining the delayed clock signal with the undelayed signal using the external logic. This application brief demonstrates how it can be done with a DS1035. The technique works with the DS1100 and DS1135 series as well. If a clock signal is delayed by one-quarter period, it can be gated with the original waveform to produce a novel application: frequency-doubled output. This time, the XOR propagation delay (tPD) will impact only the relative skew from input to output and will not otherwise distort the waveform. Obviously, the optimum delay time for this application is one-quarter of the input period. Deviation from this "ideal" value, or altering the input frequency, will cause a change in the output duty cycle but will not change the frequency. The minimum usable delay (lowest usable input frequency) is dependent only on the minimum acceptable output pulse width or duty cycle. The maximum usable delay (highest input frequency) is constrained by the minimum input pulse width specification of the delay line. 相关型号   APP 881: Dec 12, 2001 DS1004 5抽头、高速硅延迟线 完整的数据资料 (PDF, 55kB) DS1035 3合1、高速硅延迟线 完整的数据资料 (PDF, 51kB) DS1100 5抽头、经济型定时单元(延迟线) 完整的数据资料 (PDF, 168kB) 免费样品 DS1135 3合1、高速硅延迟线 完整的数据资料 (PDF, 136kB) 免费样品 自动更新 需要自动接收最新发布的应用笔记吗？请订阅EE-Mail™ (English only)。 我们期待您的反馈！ 喜欢？不喜欢？有待改善？或为我们提供建议？请与我们联系 — 我们将根据您的意见或建议改善我们的工作。 网页评价或提供建议   下载，PDF格式 (90kB)  AN881, AN 881, APP881, Appnote881, Appnote 881