Abstract: This application note describes using delay lines to correct system timing or "skew" of phased signals such as data and clock signals. Skew can be caused by signal delays in the signal path or inherent incompatibilities between system integrated circuits. In systems with distributed clocks, great care is taken to ensure phase integrity through clock distribution trees. In cases where both long and short clock runs are needed, a similar configuration to the one above can be used to delay clocks taking short routes relative to those taking longer routes. Note in this example that two successive tap outputs are used to feed the clock drivers, not the master clock and the first tap. This is because smaller delays are available tap-to-tap than from input to Tap 1, (e.g., down to 2ns for the DS1004). The smallest input to Tap 1 delay in the family is 4ns for the DS1100U-20, which may be too long unless very long runs are experienced. 相关型号   APP 879: Dec 12, 2001 DS1004 5抽头、高速硅延迟线 完整的数据资料 (PDF, 55kB) DS1004 5抽头、高速硅延迟线 完整的数据资料 (PDF, 55kB) DS1005 5抽头硅延迟线 完整的数据资料 (PDF, 63kB) DS1023 8位、可编程定时单元 完整的数据资料 (PDF, 256kB) 免费样品 DS1100 5抽头、经济型定时单元(延迟线) 完整的数据资料 (PDF, 168kB) 免费样品 DS1110 10抽头硅延迟线 完整的数据资料 (PDF, 120kB) DS1135 3合1、高速硅延迟线 完整的数据资料 (PDF, 136kB) 免费样品 自动更新 需要自动接收最新发布的应用笔记吗？请订阅EE-Mail™ (English only)。 我们期待您的反馈！ 喜欢？不喜欢？有待改善？或为我们提供建议？请与我们联系 — 我们将根据您的意见或建议改善我们的工作。 网页评价或提供建议   下载，PDF格式 (40kB)  AN879, AN 879, APP879, Appnote879, Appnote 879