Abstract: This application note lists the internal test registers in DS31256 HDLC Controller, and explains why the user should avoid using these registers. Overview The DS31256 HDLC controller has some registers that are for internal test use only (see Table 1). The user should avoid using them. Table 1. Caption Address (h) Value (h) 0050 (Test Register) 0000 04F0 to 04FF 0000 07FD to 07FF 0000 08FD to 08FF 0000 09F8 to 09FF 0000 All test registers in DS31256 are 16 bits and set to 0 with the hardware or software reset. Only the description of test register at address 0050 is shown in the data sheet. All other test registers are hidden registers and for internal test only (not shown in the data sheet). OFFSET/ADDRESS ACRONYM REGISTER NAME DATA SHEET SECTION 0050 TEST Test Register 5.4 Test register bit 0 is used by the factory-test (FT) mode to place the DS31256 in the test mode. For normal device operation, this bit should be set to 0 whenever this register is written to. Setting this bit places the RAMs into a low-power standby mode. Bits 1 to 15 is for internal (Dallas Semiconductor) test use only, not user test-mode controls. Values of these bits should always be 0. If any of these bits are set to 1, the device does not function properly. DS31256 Information For more information about the DS31256, refer to the data sheet, which is available on our website at www.maxim-ic.com/DS31256. Conclusion This application note has listed the internal test registers for the DS31256 and explained why the user should avoid using these registers. If you have further questions about our HDLC controller products, please contact the Telecommunication Applications support team via email at , or call 972-371-6555. 相关型号   APP 3071: Mar 09, 2004 DS31256 256通道、高吞吐率HDLC控制器 完整的数据资料 (PDF, 1.2MB) 自动更新 需要自动接收最新发布的应用笔记吗？请订阅EE-Mail™ (English only)。 我们期待您的反馈！ 喜欢？不喜欢？有待改善？或为我们提供建议？请与我们联系 — 我们将根据您的意见或建议改善我们的工作。 网页评价或提供建议   下载，PDF格式 (18kB)  AN3071, AN 3071, APP3071, Appnote3071, Appnote 3071