Abstract: The MAX3872 is a clock and data recovery (CDR) with limiting amplifier IC, designed to operate at multiple data rates. It is intended for regenerator and receiver applications and contains a fully integrated phase-locked loop (PLL). The PLL is a second-order feedback system that requires an external capacitor for the loop filter. This capacitor is a significant factor in multi-rate designs because it determines the acquisition time and jitter peaking at a particular data rate. This design note is intended as a guide for choosing the optimal filter capacitor to minimize acquisition time, while meeting the jitter peaking specifications at all the data rates required for the application. 你所查询的应用笔记提供Acrobat PDF格式： APPLICATION NOTE 1993:MAX3872: Choosing an Optimal Filter Capacitor for the MAX3872 Multi-Rate CDR (PDF, 56kB) 免费Acrobat PDF阅读软件可从以下网站获得： http://chinese-s.adobe.com/products/acrobat/readstep2.html 相关型号   APP 1993: Apr 24, 2003 MAX3872 多速率时钟及数据恢复，带有限幅放大器 完整的数据资料 (PDF, 1MB) 免费样品 自动更新 需要自动接收最新发布的应用笔记吗？请订阅EE-Mail™ (English only)。 我们期待您的反馈！ 喜欢？不喜欢？有待改善？或为我们提供建议？请与我们联系 — 我们将根据您的意见或建议改善我们的工作。 网页评价或提供建议   下载，PDF格式 (56kB)  AN1993, AN 1993, APP1993, Appnote1993, Appnote 1993