APP 466: Nov 14, 2001

关键词: circuit card layout, 10Gbps, 10G, current mode logic, CML, microstrip signal paths, layout geometry, crosstalk, jitter, signal integrity, deserializer, 10Gbps 1:16 deserializer, EV kit, evaluation kit
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应用笔记466

MAX3950: Printed Circuit Card Layout Considerations for 10Gbps Current Mode Logic Inputs on the MAX3950 EVKIT

Abstract: Interfacing 10Gbps current-mode logic (CML) signals using controlled-impedance microstrip signal paths on printed circuit cards requires appropriate material selection and careful attention to layout geometry in order to control crosstalk, jitter and signal integrity. The following example from the MAX3950 10Gbps 1:16 deserializer evaluation kit (EV kit) board illustrates some key points.

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APPLICATION NOTE 466: MAX3950: Printed Circuit Card Layout Considerations for 10Gbps Current Mode Logic Inputs on the MAX3950 EVKIT (PDF, 52kB)

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相关型号

APP 466: Nov 14, 2001

MAX3950

+3.3V、10.7Gbps、1:16解串器，带有LVDS输出

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(PDF, 392kB)

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AN466, AN 466, APP466, Appnote466, Appnote 466